one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ultralow power, +3.3 v, rs-232 notebook pc serial port drivers/receivers adm560/adm561 features rs-232 compatible operates with 3 v or 5 v logic ultralow power cmos: 1.3 ma operation low power shutdown: 0.2 m a suitable for serial port mice 116 kbits/s data rate 1 m f charge pump capacitors single +3 v to +3.6 v power supply two receivers active in shutdown (adm560) applications laptop computers palmtop computers notebook computers peripherals modems printers battery operated equipment general description the adm560/adm561 are four driver/five receiver interface devices designed to meet the eia-232 standard while operating with a single +3.3 v power supply. the devices feature an on- board dc-to-dc converter, eliminating the need for dual 5 v power supplies. this dc-dc converter contains a voltage doubler and voltage inverter which internally generates 6.6 v from the input +3.3 v power supply. the adm560 and adm561 consume only 5 mw making them ideally suited for battery and other power-sensitive appli- cations. a shutdown facility is also provided which reduces the power to 0.66 m w. the adm560 contains active low shutdown and active high receiver enable signals. in shutdown mode, two receivers remain active thereby allowing monitoring of peripheral devices. this feature allows the device to be shut down until a peripheral device begins communication. the active receivers can alert the processor which can then take the adm560 out of the shut- down mode. the adm561 features active high shutdown and an active low receiver enable. in this device all receivers are disabled in shutdown. the adm560/adm561 is fabricated using cmos technology for minimal power consumption. it features a high level of over- voltage protection and latch-up immunity. the receiver inputs adm560 adm561 gnd 10 shdn (adm561) shdn (adm560) 25 cmos outputs 24 r5 in r5 out r5 18 19 r4 in r4 out r4 23 22 r1 in r1 out r1 r3 in r3 out r3 27 26 9 r2 in r2 out r2 4 5 8 t1 in eia/tia-232 outputs cmos inputs t1 out t3 in t3 out t3 20 7 2 1 t1 +3.3v to +6.6v voltage doubler +6.6v to ?.6v voltage inverter 16 15 14 12 17 1 m f 10v 13 1 m f 6.3v +3.3v input v cc v+ v c1+ c1 c2+ c2 1 m f 10v 1 m f 10v t4 in t4 out t4 21 28 11 0.1 m f t2 in t2 out 6 3 t2 eia/tia-232 inputs en (adm560) en (adm561) can withstand up to 25 v levels. the transmitter inputs can be driven from either 3 v or 5 v logic levels. this allows operation in mixed 3 v/5 v power supply systems. the adm560/adm561 is packaged in a 28-pin so and a 28-pin ssop package. ordering guide model temperature range package option adm560jr 0 c to +70 c r-28 adm560jrs 0 c to +70 c rs-28 adm561jr 0 c to +70 c r-28 adm561jrs 0 c to +70 c rs-28
parameter min typ max units test conditions/comments output voltage swing 5.0 5.5 volts v cc = 3.3 v, three transmitter outputs loaded with 3 k w to ground 4 4.5 volts v cc = 3.0 v, all transmitter outputs loaded into 3 k w to ground v cc power supply current 1.3 2 ma no load, t in = v cc 2.2 3.0 ma no load,t in = gnd shutdown supply current 0.2 5 m a shdn = gnd (adm560); shdn = v cc (adm561), t in = v cc input logic threshold low, v inl 0.4 v t in, en, en , shdn, shdn , input logic threshold high, v inh 2.4 v t in, en, en , shdn, shdn logic pullup current 3 20 m at in = gnd eia-232 input voltage range C25 +25 v eia-232 input threshold low 0.4 0.8 v eia-232 input threshold high 1.1 2.4 v eia-232 input hysteresis 0.3 v eia-232 input resistance 3 5 7 k w cmos output voltage low, v ol 0.4 v i out = 1.6 ma cmos output voltage high, v oh 2.8 v i out = C40 m a cmos output leakage current 0.05 5 m a en = v cc , en = gnd, 0 v r out v cc output enable time 200 ns output disable time 300 ns receiver propagation delay tphl 0.4 1 m s tplh 1.3 2 m s instantaneous slew rate 30 v/ m sc l = 50 pf, r l = 3 k w C7 k w transition region slew rate 5.0 v/ m sr l = 3 k w , c l = 2500 pf measured from +3 v to C3 v or C3 v to +3 v transmitter output resistance 300 w v cc = v+ = vC = 0 v, v out = 2 v rs-232 output short circuit current 10 ma specifications subject to change without notice. adm560/adm561Cspecifications rev. 0 C2C (v cc = +3.3 v 10%, c1Cc4 = 1 m f. all specifications t min to t max unless otherwise noted.) absolute maximum ratings* (t a = +25 c unless otherwise noted) v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v v+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (v cc C0.3 v) to +14 v vC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to C14 v input voltages t in . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to (v+, +0.3 v) r in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 v output voltages t out . . . . . . . . . . . . . . . . . . . (v+, +0.3 v) to (vC, C0.3 v) r out . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to (v cc +0.3 v) short circuit duration t out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous power dissipation ssop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mw soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mw operating temperature range commercial (j version) . . . . . . . . . . . . . . . . . .0 c to +70 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 sec). . . . . . . . . . . . . +300 c esd rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2000 v *this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specifica- tion is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
adm560/adm561 rev. 0 C3C table i. adm560 adm561 shdn = 1 shdn = 0 normal operation en = 1 receivers active en = 0; receivers active en = 0 receivers inactive en = 1; receivers inactive shdn = 0 shdn = 1 shutdown mode en = 1 receivers r1Cr3 inactive en = 0; receivers inactive en = 1 receivers r4 & r5 active en = 1; receivers inactive en = 0 receivers r1Cr5 inactive pin function description mnemonic function v cc power supply input 3.3 v 10%. v+ internally generated positive supply (+6.6 v nominal). vC internally generated negative supply (C6.6 v nominal). gnd ground pin. must be connected to 0 v. c1+, c1C external capacitor 1 is connected between these pins. c2+, c2C external capacitor 2 is connected between these pins. t in transmitter (driver) inputs. these inputs accept 3 v or 5 v logic levels. an internal 400 k w pull-up resistor to v cc is connected on each input. t out transmitter (driver) outputs (typically 6 v). r in receiver inputs. these inputs accept rs-232 signal levels. an internal 5 k w pull-down resistor to gnd is connected on each of these inputs. r out receiver outputs. these are 3 v logic levels. en/ en receiver enable (active high on adm560); active low on adm561) refer to table i. shdn /shdn shutdown control (active low on adm560); (active high on adm561) refer to table i. pin configurations 1 2 3 7 28 27 26 22 8 9 10 21 20 19 11 12 18 17 4 5 25 24 6 23 top view (not to scale) 13 14 16 15 adm560 adm561 r2 out r2 in r5 in t4 in r3 in t1 out t2 out t3 out t4 out r5 out v+ v v cc c1+ c1 c2+ c2 gnd shdn (adm560) shdn (adm561) r3 out t3 in r4 in r4 out r1 in r1 out t1 in t2 in en (adm560) en (adm561)
rev. 0 C4C adm560/adm561 general description the adm560/adm561 are rs-232 transmission line drivers/ receivers which operate from a single +3.3 v supply. this is achieved by integrating step up voltage converters and level shifting transmitters and receivers onto the same chip. cmos technology is used to keep the power dissipation to an absolute minimum. the adm560/adm561 is a modification, enhance- ment and improvement to the ad230Cad241 family and derivatives thereof. it is essentially plug-in compatible and does not have materially different applications. the adm560/adm561 contains an internal voltage doubler and a voltage inverter which generates 6.6 v from the +3.3 v input. four external 1 m f capacitors are required for the internal voltage converter. circuit description the internal circuitry consists of three main sections. these are: 1. a charge pump voltage converter 2. 3 v logic to eia-232 transmitters 3. eia-232 to 3 v logic receivers. charge pump dc-dc voltage converter the charge pump voltage converter consists of an oscillator and a switching matrix. the converter generates a 6.6 v sup- ply from the input +3.3 v level. this is done in two stages using a switched capacitor technique as illustrated below. first, the 3.3 v input supply is doubled to 6.6 v using capacitor c1 as the charge storage element. the 6.6 v level is then inverted to gen- erate C6.6 v using c2 as the storage element. capacitors c3 and c4 are used to reduce the output ripple. their values are not critical and can be reduced if higher levels of ripple are acceptable. the charge pump capacitors c1 and c2 may also be reduced at the expense of higher output imped- ance on the v+ and vC supplies. the v+ and vC supplies may also be used to power external circuitry if the current requirements are small. transmitter (driver) section the drivers convert 3 v or 5 v logic input levels into eia-232 output levels. with v cc = +3.3 v and driving an eia-232 load, the output voltage swing is typically 5.5 v. s1 s3 v+ = 2v cc s2 s4 internal oscillator c1 c3 v cc gnd v cc figure 1. charge pump voltage doubler s1 s3 s2 s4 internal oscillator c2 c4 v? = ?(v+) gnd v+ gnd from voltage doubler figure 2. charge pump voltage inverter unused inputs may be left unconnected, as an internal 400 k w pull-up resistor pulls them high forcing the outputs into a low state. the input pull-up resistors typically source 8 m a when grounded so unused inputs should either be connected to v cc or left unconnected in order to minimize power consumption. receiver section the receivers are inverting level shifters which accept eia-232 input levels and translate them into 3 v logic output levels. the inputs have internal 5 k w pull-down resistors to ground and are also protected against overvoltages of up to 25 v. the guaranteed switching thresholds are 0.4 v minimum and 2.4 v maximum. unconnected inputs are pulled to 0 v by the internal 5 k w pull-down resistor. this, therefore, results in a logic 1 output level for unconnected inputs or for inputs connected to gnd. the receivers have schmitt trigger input with a hysteresis level of 0.3 v. this ensures error-free reception for both noisy inputs and for inputs with slow transition times. enable and shutdown table i shows the truth table for the enable and shutdown con- trol signals. when disabled, all receivers are placed in a high impedance state. in shutdown, all transmitters are disabled and all receivers on the adm561 are disabled. on the adm560, receivers r4 and r5 remain enabled in shutdown.
adm560/adm561 rev. 0 C5C typical performance curves 6 0 3000 3 1 500 2 0 5 4 2500 2000 1500 1000 load capacitance ?pf v oh ?volts 20kbps 80kbps 160kbps t a = +25 c v cc = +3.3v 4 transmitters loaded with rl = 5k w || cl c1 ?c4 = 1? figure 3. transmitter output voltage high vs. load capacitance 6.25 4.75 5 5.25 0 5.75 34 2 1 | i out | ?ma | t out | ?volts t a = +25 c c1 ?c4 = 1? v cc = +3.3v transmitters unloaded t out high t out low figure 4. transmitter output voltage vs. load current 10.5 3.5 5.5 5.5 2.5 7.5 6.5 8.5 9.5 5.0 4.5 4.0 3.5 3.0 4.5 v cc ?volts v oh ?volts 1 transmitter loaded 4 transmitters loaded t a = +25 c c1 ?c4 = 1? transmitters loaded with 5k w || 2500pf figure 5. transmitter output voltage high vs. v cc 0 ? 3000 ? ? 500 ? 0 ? ? 2500 2000 1500 1000 load capacitance ?pf v ol ?volts 160kbps 80kbps 20kbps t a = +25 c v cc = +3.3v 4 transmitters loaded with rl = 5k w || c l c1 ?c4 = 1? figure 6. transmitter output voltage low vs. load capacitance 7.5 2.5 3000 5.5 3.5 500 4.5 0 6.5 2500 2000 1500 1000 load capacitance ?pf slew rate ?v/? t a = +25 c v cc = +3.3v r l = 5k w c1 ?c4 = 1? 3 transmitters loaded 4 transmitters loaded figure 7. transmitter slew rate vs. load capacitance ? ?0 5.5 ? ? 3.0 ? 2.5 ? ? ? 5.0 4.5 4.0 3.5 v cc ?volts v ol ?volts t a = +25 c c1 ?c4 = 1? transmitters loaded with 5k w || 2500pf 4 transmitters loaded 1 transmitter loaded figure 8. transmitter output voltage low vs. v cc
rev. 0 C6C adm560/adm561 printed in u.s.a. c1940C5C7/94 outline dimensions dimensions shown in inches and (mm). 28-lead so (r-28) 0.019 (0.49) 0.014 (0.35) 0.05 (1.27) bsc 0.708 (18.02) 0.696 (17.67) 0.01 (0.254) 0.006 (0.15) 0.096 (2.44) 0.089 (2.26) 0.013 (0.32) 0.009 (0.23) 0.042 (1.067) 0.018 (0.457) 6 0 0.03 (0.76) 0.02 (0.51) pin 1 0.299 (7.6) 0.291 (7.39) 0.414 (10.52) 0.398 (10.10) 15 14 1 28 1. lead no. identified by a dot. 28-lead ssop (rs-28) 1. lead no. 1 identified by a dot. 2 leads will be either tin plated or solder dipped 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) 8 0 0.0256 (0.65) bsc 0.407 (10.34) 0.397 (10.08) 0.008 (0.203) 0.002 (0.050) 0.07 (1.78) 0.066 (1.67) pin 1 15 14 1 28 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.207) 10 ?0 ? 0 0 5 20 15 13 10 5 25 current ?ma output voltage v+, v? ?volts v+ and v equally loaded v+ loaded no load on v v?loaded no load on v+ t a = +25 c v cc = 3.3v c1 ?c4 = 1? all transmitters unloaded figure 9. v+, vC vs. load current
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